The microprocessor is Adaptive Epic
Processor with two parts. A general purpose
processor and adaptive hardware, wherein the
"architecture" can be customized under
compiler control. It supports several novel
features such as predicated execution, control
speculation, and compiler controlled caches.
HPL-PD serves to characterize this processor
space.
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We innovate
hardware based cache smart cache management
features and strategies for managing programmable caches.
Program profiling plays an integral role in these
efforts.
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The code runs on
the target processor via the constraint-sensitive
instruction scheduling. The issue of power constraints
on the target processor is also addressed by our
research.
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