VISION

MISSION

TECHNOLOGY

FRAMEWORK

RESEARCH AREAS

       HW/SW RTOS

       TIMEC-TIME TRACT

       ADAPTIVE EPIC

       RCSP

       POWER AWARE        COMPILERS

       COMPILER CONTROLLED
       CACHES

Reduced Configuration Space Processor and its Programming Environment

RCSP has a core processor based on ILP technology and a configurable accelarator. The configurable accelarator is aimed at providing predictable performance improvements to application kernels such as the IDCT routine from MPEG or the corner-turn procedure from the NBRADAR application.

Speedup on Sample Applications

The core processor "signals" the configurable accelarator when the kernel (such as IDCT) needs to be executed. The configurable hardware will then automatically load the configuration, excute the routine, and signal the core processor when it is done. This is not too different from a procedure call. The core processor and the configurable computing engine (CCE) share the memory hierarchy.

Our group is intersted in researching techniques for partitioning the program between the core processor and the CCE, optimizing the execution along each path, as well as automatically generating code for the RCSP (machine=core processor+CCE). The "reduced configuration space" helps contain compilation costs by limiting the set of choices to a small family of widely used primitive functions such as an IDCT or FFT.