VISION

MISSION

TECHNOLOGY

FRAMEWORK

RESEARCH AREAS

       HW/SW RTOS

       TIMEC-TIME TRACT

       ADAPTIVE EPIC

       RCSP

       POWER AWARE        COMPILERS

       COMPILER CONTROLLED
       CACHES

Research Areas

Language Support
Compiler Optimizations
Adaptive Architecture
Hardware/Software Real-Time Operating Systems
 

Language Support

Language Support is mechanisms for specifying constraints of various kinds like timing, power and memory footprint. In the embedded application program that is being developed. For instance, timing constraints indicate the amount of time that ought to elapse between the events that occur at certain program points. We have developed compiler tools based on a language extension called TimeC that are aimed at using these constraints to restructure the program. The goal of this restructuring (optimization) is to meet the timing constraints and report success or failure to achieve this (analysis) to the programmer. A significant goal has been to design languages and mechanisms without adding substantial complexity to the optimization and analysis phases. Our current work on seeks to provide a similar treatment of power constraints.

Compiler Optimizations

In the past, we have developed compiler optimizations that go beyond traditional data and control-dependences. Our technologies have focused on additional optimizations, Time-constraint Driven RA and Scheduling. 

We are currently studying optimizing compiler based techniques for power-aware computing. We are also involved in a major effort at developing compiler-centric techniques for managing programmable caches in order to efficiently execute data intensive applications whose memory access patterns are irregular. An important component of this research is considering applications running on EPIC architectures, which are expected to form the cores of the next generation of System-On-a-Chip (SOC) environments.
Compiler Optimizations for Power Aware Computing (COPAC)
Algorithmic Strategies for Compiler Controlled Caches (C3) 

Adaptive Architectures

A central theme of our research is concerned with EPIC architectures augmented with reconfigurable hardware. We believe this will be the domineering platform for significant classes of future embedded applications. The goal is to consider hardware features - including those concerning reconfigurablility.

Hardware/Software Real-Time Operating System

Traditionally, designers make hardware and software partitioning decisions at an early stage in the design, with the development of each part independent from there on. Hardware-software codesign provides a more flexible design process, with tradeoffs and feedback between the two being made throughout. Thus the result is a design improved in many areas -- performance, programmability, area, maintenance, reliability, etc. Hardware-software codesign has the potential to make high-level synthesis much more widely used by providing for rapid prototyping. For example,instead of synthesizing down just to an ASIC, one could synthesize down to ASIC-microprocessor combinations.The timing critical parts would be partitioned to the hardware (say, an FPGA) with the rest in software. With the low price of many microprocessors, areas such as embedded system design would benefit greatly from automated tools for designing systems of interacting hardware and software.