VISION

MISSION

TECHNOLOGY

FRAMEWORK

RESEARCH AREAS

       HW/SW RTOS

       TIMEC-TIME TRACT

       ADAPTIVE EPIC

       RCSP

       POWER AWARE        COMPILERS

       COMPILER CONTROLLED
       CACHES

Power-Aware Compilers

We are developing software techniques for application-managed power-aware computing. The focus is on trading quality-of-service (QoS) metrics such as precision and performance in favor of power and vice-versa. The strategy is to innovate a range of compiler optimizations based on instruction scheduling, loop transformations including loop-invariant code motion and other optimizations to help find solutions satisfying the power-QoS expectations. We are also developing compiler transformations that exploit energy optimizing technology features such as gated clocks, variable power supply, threshold voltage logic and variable frequency clocks. These transformations will be validated on simulation models and the strongARM architecture in collaboration with Intel.

This research is supported by the DARPA Power-Aware Computing/Communication program under the contract F30602-00-2-0564.