VISION

MISSION

TECHNOLOGY

FRAMEWORK

RESEARCH AREAS

       HW/SW RTOS

       TIMEC-TIME TRACT

       ADAPTIVE EPIC

       RCSP

       POWER AWARE        COMPILERS

       COMPILER CONTROLLED
       CACHES

Compiler-Controlled Cache Management

We are innovating algorithmic strategies for managing programmable caches. The intent is to overcome significant hurdles to performance germane to data-starved applications. Additionally, this effort also aims to identify hardware-based smart cache management features and validate them via industry-strength simulation and emulation. Of particular interest is the next generation of COTS microprocessors based on EPIC technology ; the IA-64 architecture co-developed by HP and Intel and embodied in the Merced processor.