VISION

MISSION

TECHNOLOGY

FRAMEWORK

RESEARCH AREAS

       HW/SW RTOS

       TIMEC-TIME TRACT

       ADAPTIVE EPIC

       RCSP

       POWER AWARE        COMPILERS

       COMPILER CONTROLLED
       CACHES

Adaptive EPIC Architectures

Poor scalability of superscalar archtectures with increasing instruction level parallelism has resulted in a trend towards statically scheduled horizontal architectures such as Very Large Word Instruction (VLIW) processors and their more sophisticated successors, namely EPIC architectures. We are investigating the means for extending the the EPIC model with ability to reconfigure the datapath at runtime in terms of the number and types of the functional units comprising it.

Our motivation is to combine the advantages of the EPIC style architecture (simpler architecture, known compilation technology) and those of reconfigurable logic (fine-grained parallelism, explicit control over micro-architectural features). The conceptual vehicle for this research is the Adaptive EPIC class of machines that we have proposed. An adaptive EPIC processor executes mutiple independent instructions (as specified by the compiler) every cycle. However, unlike in the standard VLIW processor, some of these instructions will execute on functional units configured dynamically on a reconfigurable logic resource.

A previous effort on this topic called Reduced Configutation Space Processor was supported by the DARPA Adaptive Computing Systems program under the contract DABT63-96-C-0049.